In a central processing unit (CPU), the operations of various logical components are controlled by a system clock which is generally generated utilizing a phase-lock loop (PLL). The operations of the various logical components are interrelated and, hence, various circuit path timing constraints typically exist. The actual timing associated with the circuit paths during operation of the CPU may depend upon the voltage supplied to the various components of the CPU. To ensure that the timing constraints are satisfied and that the CPU operates as expected, the frequency of the system clock may be selected according to worst-case criteria. In a relatively large and complex CPU, the supply voltage supplied to various components of the CPU may vary for a variety of reasons. If the frequency of the system clock is selected according to the worst-case criteria for all of the various components, system performance may be appreciably restricted.